Basic Timing; Read/Write Cycles - Toshiba TLCS-90 Series Data Book

TOSHIBA
TMP90C840
3.2 Basic Timing
Each instruction of the TMP90C840 is executed by combination of read,
write and dummy cycles. These are basic cycles that synchronize with
the system clock. 1/2 of the frequency of the clock oscillation is used
as the sys tem clock; e. g., if the clock freq uency is 10 MHz, the
frequency of the system clock is 5 MHz. The system clock cycle is also
called a "state".
The TME90C840 bus operation are basically synchronous, and each of
memory read, memory write and dummy cycles is completed in two states,
unless they are not requested to wait.
The "CLK" pin generates a pulse at a frequency that further halves the
frequency of the system clock. This CLK signal synchronizes with the
bus cycles with no wait request.
3.2.1 Read/Write cycles
Fig. 3.2.(1) is a
t~m~ng
chart of external memory read/write cycles.
The left side shows the bus operation timing with no wait request, and
on the right side shows that with a 2-state wait request.
Each wait consists of a mUltiple of two states, making a bus cycle
wait for two, four, six, eight states, etc •..•
State
E ~
Xl
CLK
A¢ - 19
[
RD
Read
Cycle
D¢ - 7_
WAIT
Fig. 3.2.(1) Timing of External Memory Read/Write Cycles
MPU90-24