Standby Function - Toshiba TLCS-90 Series Data Book

TOSHIBA TMP90C840
3.4 Standby Function
When a HALT instruction is executed, the TMP90C840 selects one of the
following modes as determined by the halt mode set register:
(1)
RUN
(2) IDLE.l
(3) IDLE2
(4)
STOP
Suspends only the CPU operation.
remains unchanged.
The power consump t ion
Sus pends all interna 1 circui t s except the interna 1
osc illator. In this mode, the power consumpt ion is les s
than 1/10 of that in the normal operation.
Operate only the internal oscillator and specific internal
I/O devices. The power consumption is less than
1/
3 of
that in the normal operation.
Suspends all internal
oscillator. In this
considerably reduced.
circuits including the internal
mode, the power consumption
1S
The HALT mode set register (HALTM) is assigned to the bits 2 and 3 of
the memory address FFD2H in the internal I/O register area (other bits
are used to control other functions). The register is reset to "00"
(RUN mode) by resetting.
These HALT state can be released by resetting or requesting an
interrupt. Either a non-maskable or maskable interrupt is acknowledged
and processed if the CPU executes the EI (enable interrupt) instruction.
However the CPU executes the DI (disable interrupt) instruction, a
maskable interrupt may be accepted, and the CPU starts execut ing the
instruction following the HALT instruction.
7
6
5
4 3
2
1 0
WDMOD IWDTE
WDTOUT
I WARM
HALTM EXF IDRVE
(FFD2H) I
I I I I I
See "3.10 Watchdog Timer"
I I I I
- )
See "3.4.4 STOP mode
II
I I I
I I I
)
Exchange flag
I I
See "3.1.2 Registers"
I I
0 0 RUN
0 1 STOP
1
0 IDLE 1
1 1
IDLE2
Fig. 3.4 (1) HALT Mode Set Register
MPU90-49