Control Registers - Toshiba TLCS-90 Series Data Book

TOSHIBA TMP90C840
3.10.1 Architecture
Fig. 3.10 (1) is a block diagram of the watchdog timer (WDT).
The watchdog timer consists of a 20-stage binary counter (input clock:
o @fc/2), a flip-flop that disables/enables the selector, a selector
that selects one of the four output clocks generated from the binary
counter, and two control registers.
INTWD Interrupt
Selector
enable
¢
(fc/2)
Twenty-stage Binary
Counter for Watch Dog
Timer
Reset
Under Execution --------~
of HALT Instruction
(stop Mode)
Write
'4EH'
Watch Dog Timer
control Register
(WDCR)
Internal Data Bus
R
Q
F/F
Reset
'-----'"-........ :- WDTE
Fig. 3.10 (1) Block Diagram of Watchdog Timer
3.10.2 Control Registers
WDT is controlled by two control registers (WDMOD and WDCR).
(1) Watchdog timer mode register (WDMOD)
1 Set the detecting time of watchdog timer (WDTP)
The WDT interrupt period is set by this 2-bit flag. WDTP is
i~!tialized
to "00" by resetting, providing the initial set value of
2 /fc (sec.) (approx. 8,192 states).
MPU90--129