Interrupt Acknowledge Timing - Toshiba TLCS-90 Series Data Book

TOSHIBA TMP90C840
3.2.3
Interrupt Acknowledge Timing
Fig.
3.2
(4) shows the basic tlmlng of interrupts being acknowledged.
An interrupt request may be sampled by the CPU at the falling edge of
the CLK signal in the last bus cycle of each instruction. Note,
however, that the sampling of a non-maskable interrupt (NMI) is
delayed a half the system clock cycle.
Xl
When an interrupt request is acknowledged, the CPU starts an interrupt
response sequence that proceeds as follows: 1) A read cycle (In this
cycle·, the read data is not used in the CPU because the pipel ine
processing prefetches instructions. The pipeline processing is
described in
"3.2.6
Bus Operation for Executing Instructions".),
2)
two dummy cycles (the CPU receives an interrupt vector from an
internal interrupt controller), 3) out put
0
f the interrupt vec tor
(OOOH
for the upper address locations A8 to A19) and read out of the
dummy cycle,
4)
one dummy cycle,
5)
saving the contents of the program
counter PC and those of the register pair AF into the stack (four
write cycles), and
6)
the CPU resets the interrupt enable flag IFF to
"0" (to disable interrupts) and jumps to the interrupt processing
routine.
If a "micro DMA processing" is specified as
follows the sequence to be described in
"3.3.2
-, Jl
Jl Jl
L.n IJl
Jl Jl Jl
the interrupt, the CPU
Micro Dt'1A processing".
ir-1'
Jl
ir-1'
Jl
'J
CLK
I ~ I
\
I
\
A¢ - 19
RD
WR
D¢ - 7
NMI
INT¢
(Level)
INT¢·1·2
(Rising Edge)
Internal INT
-K
-
Last
\
\
/ i\
I
Last Instructlon
Execution Cycle
X
I
J
- ---
Next + 1
~
Dummy
\
----
J
---
~
..
--
---- ---
~
Interrupt Acknowledge
Sequence
Fig.
3.2 (4)
Interrupt Acknoledge Timing
MPU90-26
C
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