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TOSHIBA
TMP90CS40
®
The other slave controllers (with the WU bit remalnlng at "I ") ignore
the receiving data because their MSBs (bit S or RBS) are set to "0" to
disable the interrupt INTRX.
When the WU bit is cleared to "a", the interrupt INTRX occurs, making
it possible to read the receiving data.
Only when
WU
=
0,
the slave controllers can transmit data to the
master
controller,
including
those
indicating
the
end
of
data
receiving.
Example:
Link
two
slave
controllers
serially
with
the
master
controller, and use the internal clock
01
as the transfer
clock.
t
,
TxD
RxD
Haster
o
Set the master control
Main
P3CR
<-
- 0 0
1
1
0
INTEL
<- -
1 1
SCCR
(-
x x x x x x x a
SCMOD
(- 1 0 1
a l l 1 a
SCBUF
<-
a 0 a a a 0
o
1
INTTX interrupt
I-SCMOD (- a
I_SCBUF
<-
* * * * * * *
*
o
Set the slave controller 2
Main
I-P3CR
<--
I
INTEL
<-
1 1
a
1
a
1 1
x x x x x x x a
a a
1 1 1 1
1 a
I
SCCR
<-
I_SCMOD
<-
AA
~
~
,~
~
TxD
RxD
TxD
RxD
Slave 1
Slave 2
Select Code Select Code
00000001
00001010
Select P32 as TxD and P31 as RxD.
Enable INTRX and INTTX.
Disable the hand-shake function.
Select
01
as the transfer clock in the
9-bit UART mode.
Set the select code for the slave con-
troller
1.
Set TBS to "a".
Set data for transmission.
Select P33 as TxD and P3l as RxD.
Enable INTRX and INTTX.
Disable the hand-shake function.
Set WU to 1 in the 9-bit UART mode
(transfer clock:
01) •
MPU90-124
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