Toshiba TLCS-90 Series Data Book page 164

TOSHIBA
TMP 804 9P I -6, TMP 8039PI-6
Reading of Internal Program Memory
The processor is placed in the READ mode by applying +12V to the EA pin and
OV to the RESET pin. The address of the location to be read is then
applied to BUS and the low order 2-bits of Port 2. The address is latched
by a 0 to 1 transition on RESET and the high level causes the contents of
program memory location addressed to appear on the eight lines of BUS.
• Figure 7 illustrates the timing diagram for this operation.
(S)
Single Step Operation.
• A single step feature useful for debug can be implemented by utilizing a
circuit shown in Figure 8
(a)
combined w.ith the SSpin and ALE pin.
• A D-t1Ee flip flop with set and reset is used to generate SS. In the run
mode SS is held high by keeping the flip flop set. To enter single step,
set is removed allowing ALE to bring SS low via reset input. The next
instruction is started by clocking a "1" into the FF which will not appear
on
55
unless ALE is high removing reset. In response to SS going high
the processor begins an instruction fetch which brings ALE low resetting
FF and causing the processor to again enter the stopped state.
• The timing diagram in this case is as shown in Figure 8 (b). (EA 5V).
(6)
Lower Power Stand-by Mode.
• The Lower TMP8049 has been organized to allow power to be removed from all
but the volatile, 128 x 8 data
RAM
array. In power down mode the contents
of data RAM can be maintained while drawing typically 10 - 15% of normal
operating power requirements.
• vee serves as the 5V supply for the bulk of the TMP8049 while the
VDD
supplies only the RAM array. In standby mode vee is reduced to ov but VDD
is kept at 5V. Applying a low level to reset inhibits any access to the
RAM by the processor and guarantees that RAM cannot be inadvertently
altered as power is removed from vee.
ALE
DBO - DB7
P20 - P23
___ I
\~-----------------------------------
\ /
; : For two
~----------~ ~----------~
Instruction Input instruction
--A-d-d-r-e-s-s--(P-C-)-------~------~(~--A-d-d-r-e-s-s--(-P-e-~-l-)----------
Address (PC) )(
)(~
__ A_d_d_r_e_s_s __ (_P_e+_l_) __________ _
Port 20 - 23
Data
Fig.8(b) Single Step Operation Timing
MCU48-1S4