Toshiba TLCS-90 Series Data Book page 308

TOSHIBA
Data received and transmitted are stored
buffer registers to allow independent
(Full-duplex).
temporarily
tr an smis s ion
into
and
TMP90C840
separate
receiving
In the I/O interface
to the single SCLK
mode, however, the data transfer is half-duplex due
(serial clock) pin is used for transmisison and
receiving.
Two pins are provided for receiving (RxD, also used as P30 and P3l) and
transmission (TxD, also used as P32 and P33), which allows two serial
transmi~ison/receiving
using the time-sharing technique. The pin
function is selected by the P3CR registers. For example, P30 can be
used as the RxD pin by setting P3CR1, 0 to 01.
The receiving buffer register has a double-buffer structure to prevent
overruns. The one buffer receives the next frame data while the other
buffer
store~he
receive data is read by the CPU.
The use of CTS and RTS allows to halt the data transmission until the
CPU completes reading of the receive data for each frame (Hand-shake
function) .
In the UART mode, a check func t ion is added not to s tart the receiving
operation by error start bits due to noise. The channel starts
receiving data only when the start bit is detected to be normal at least
twice in three samplings.
~nen
an request is issued to the CPU to transmit data after the
transmitting buffer becomes empty or to read data after the receiving
buffer completed to store data, the interrupt INTTX or INTRX occurs
respectively. In receiving data, the occurrence of an overrun error,
parity error or framing error sets the flag (SCCR4, 3 or 2) accordingly.
MPU90-110