Toshiba TLCS-90 Series Data Book page 279

TOSHIBA TMP90C840
CD
Timer registers
®
8-bi t regi s ter s are provided to se t the interva I time. When the se t
value of a timer register matches that of an up-counter, the match
signal of their comparators turn to the active mode. If "OOH" is set,
this signal becomes active when the up-counter overflows.
Comparators
A comparator compares the values in an up-counter and a timer
register. When they matches, the comparator clears the up-counter to
"0", . and
generates an
interrupt signa I (INTTn) . If the timer
flip-flop inversion is enabled by the Timer Flip-Flop control
register, the comparator inverts the Timer Flip-flop.
CD
Timer flip-flops (Timer F/Fs)
The status of the Timer Flip-flop
1.5
inverted by the match signal
(output by comparator). Its status can be output to the timer output
pin TOI (also used as P60) and T03 (used as P70 or P80).
A Timer F/F is provided to each of the timer pairs Timer a - Timer 1
and Timern 2 - Timer 3, and is called TFFI and TFF3, respectively.
The status of TFFI is output to Tal, and that of TFF3 to T03. T03 has
2 pins (P70 and P83). P83 is selected only when the port 7 is used as
a stepping motor control port.
The Timer F/Fs are controlled by a timer flip-flop control register
(TFFCR) .
In the case of TFFI (timer F/F for the Timer a and Timer
1),
the
flip-flop operation is described as follows:
TFFCRO (FFIIS) selects the signal for inversion of TFFI. In the 8-bit
timer mode, inversion is enabled by the match signal from Timer a if
this bit is set to "1", or by the signal from Timer 1 if set to "0".
In any other mode, FFIIS must be always set to "1". It is initialized
to "0" by resetting.
TFFCRI (FFIIE) controls the inversion of TFFI. Setting this bit to
"1" enables the inversion and setting it to "0" disable.
FFIIE is initialized to "0" by resetting.
The bits TFFCR3 and TFFCR2 (FFIC) are used to set/reset TFFI or enable
its inversion by software. TFFI is reset by writing "00", set by "01"
and inverted by "10".
Similarly, TFF3 is controlled by TFFCR7 - 4.
The 8-bit timers operate as follows:
(1) 8-bit timer mode
The four interval timers 0, 1, 2 and 3 can operate independently as an
8-bit interval timer. Only the operation of Timer 1 is described
because their operations are the same.
aD
Generating interrupts at specified intervals
Periodic
interrup~s
can be generated by using Timer 1 (INTT1) in the
following procedure: Stop Timer 1, set the desired operating mode,
input clock and cycle time in, the registers TMOD, TCLK and TREGI
enable INTT1, and start the counting of Timer 1.
MPU90-81