Toshiba TLCS-90 Series Data Book page 281

TOSHIBA
TMP90CS40
~Jp-
¢Tl
TRUNl . - - J ¢ 2
BIT7 ~ 2
COt;:1ter
BITl _ _ _ --+_~...,..~
BITO 0
Cor.:?arator
"':'ir::ing
Comparator Output
(Match signal)
--------------f....I
INTTl
UC Clear
TFFl
~l--------------~r---
TOl
I
11
2.4
)Js @fc =
1011Hz
~'--_-_---...JI
I
..
:
Fig. 3.6 (7) Pulse Output (50% duty) Timing Chart
CD
Making Timer 1 count up by match signal from Timer
a
comparator.
Select the S-bit timer mode, and the set output of Timer
a
comparator
as the input clock to Timer 1.
Timer
a
n n
Comparator Match Signal - - - - - ' - - - - - - - - - - - - ' ... - - - - - - -
Up-Counter of
Timer 0
(TREGO
=
5)
Up-Counter of
---------'""X X
Timer 1 1 2 1
(TREGI
=
2) ' -_ _ _ _ _ _ _
..J ' - - - - - - -
Match Signal
from Timer 1
______________________
~n~
______ _
Fig. 3.6 (S)
®
Software inversion
The timer flip-flops can be inverted by software independent of the
timer operation.
Writing "10" into the bits TFFCR3 and TFFCR2 inverts TFFl, and writing
the same into TFFCR7 and TFFCR6 inverts TFF3.
CD
Initial setting of Timer Flip-Flops
The Timer Flip-flops can be initialized to either
"011
or "1" without
regard to the timer operation.
TFFI is initialized to
"a"
by writing "00" into TFFCR3 and TFFCR2, and
"I" by writing "01" into these bits.
(Note) Reading the data from the Timer Flip-flops and timer registers is
prohibited.
MPU90-S3