Instructions - Toshiba TLCS-90 Series Data Book

TOSHIBA
TMP90C840
In the index addressing mode, a carry resulted from calculating the
16- bit offset address is ignored; i. e., it is not added to the bank
address.
Example: LD A, (IY+23H)
Memory
CPU
1
A
45
1<-1------
1 1 45
60013H
1
1
BY
1
6
1
IY
1
F F F 0
1 1
---------------------------1
In this example, "45H" in the address 60013H is loaded into Register
A.
In any other addressing mode that accesses a non-extended data area
(the index register IX or IY is not used for address computing of the
operand), the 4-bit bank address (address bus A16 to A19) becomes "0",
indicating that the access range is from OOOOOH to OFFFFH.
(Note) Given "FFECH" to the IX value of (BX address) an instruction "LD
(IX), x", the normal write cycle is not performed, making the
result indefinite.
3.1.4 Instructions
The TMP90C840 supports a rich variety of addressing modes as well as
powerful instruction sets. There are 163 basic instructions as
categorized into the following nine groups:
o 8-bit transfer instruciton
o 16-bit transfer instruciton
o Exchange, block transfer and search instructions
o 8-bit arithmetic and logical operation instruction
o Special operation and CPU control instructions
o 16-bit arithmetic and logical operation instruciton
o Rotate and shift instructions
o Bit manipulation instruction
o Jump, call and return instruction
Table 3.1
(1)
lists the 163 basic instructions.
describes the mnemonics and their meaning.
(1) 8-bit transfer instruction
Table 3.1. (2)
The 8-bit transfer instructions inclued those for transferring 8-bit
data between registers, register and immediate address, register and
memory, or memory and immediate address.
MPU90-17