Toshiba TLCS-90 Series Data Book page 18

TOSHIBA TMP 8048A/TMP 80 35A, TMP 8049A/TMP 80 39A
ANt, ORt
Internal ·Bus---1-..A--f 0
Q
D-Type
Flip-Flop
+SV +5V
CLK Q
~+----~
Write
Puls~---+~--------------~
Inter Buffer
IN
SOkn
Fig.l Input/Output Circuit of Port 1, Port 2
SOkn I/O pins
Portl or 2
• Reset initializes all lines to a high impedance "1" state.
• When external data memory area is not addressed during execution of an
internal program, Port 0 (DBO - DB7) becomes a true bidirectional port
(bus) with associated input and output strobes. If bidirectional
feature not needed Bus can serve as either a statically latched output
port or a non-latched input port. However, I/O lines of this port
cannot be intermixed.
• As a static port data is written and latched using the OUTL instruction
and inputted using the INS instruction these two commands generate
pulses on the corresponding
RD
and WR strobe lines.
• As a bidirectional port the MOVX instructions are used to read and
write the port which generate the RD and
~
strobes.
• When not being written or read, the Bus lines are in a high impedance
sta te.
(4) Timer/Event Counter
• The 8-bit binary up counter can use either of the following frequency
inputs
(1) Internal clock (1/480 of
asc
frequency)
•••••••••••••• Timer mode
MCU48-8