Toshiba TLCS-90 Series Data Book page 148

TOSHIBA
BLOCK
DIAGRAM
Oscilla tion
Frequency
DBC-DB7
Decoder t====~
XTAL
2
Accumula tor
Bit Test
Control and Timing Circuit
XTAL 1
mET lifT
EA
55
ALE
PSEN RD Wit
PROG
------
H
0
:::0 HH O-t'!j
en
r'"> CIl"'C:! '='
tr.t'!1
~
til
It)
= =
,.., :<
.....
Cl 0-
rT "'"
Cl
~~
""
n
til
"",.,
It) rT
=
rTo-
,..,
0
rT
c: .....
It)
c:
It)
til
It)
OQ
n "'"
o
OQ
Ol
o
Cl
,.,
~ rT
rT'"
til ..,
~
:Tit)
0'"""
0' " =
til ~
,..,
= til til til
Ol
en
It)
0-
Ol
H
C
enOl
en
til
51
rT
til
,.,
= "0 III ~
en
rT
,..,
..,
0
""
rT
~
rT
,..,
0 ,..,
c:
til> til
0
0' "
,.,
n
0- "0 0'" til
rTl
til
CIl
MCU48-138
Note
Note
TMP 8049PI -6, TMP 8039PI-6
2
l-f.ask ROM
lK
x
8
(Program
Area)
64
x
8
Circuit
1)
The lower order 4 bits of
port 2 output latch are
used also for input/output
operations with the
I/O
expander.
2) The output latch of port 0
is also used for address
output.