Toshiba TLCS-90 Series Data Book page 315

TOSHIBA TMP90CB40
2) In case of asynchronous communication (UART) mode
The receiving control features a circuit for detecting the start bit
by the rule of majority.
When two or more "0" are detected during 3
samples, it is recognized as normal start bit and the receiving
operation is started.
Data being received are also evaluated by the rule of majority.
CD
Receiving buffer
The receiving buffer has a double-buffer structure to prevent
overruns. Received data are stored into the Receiving buffer 1 (shift
register type) for each 1 bit. When 7 or B bits data are stored in
the Receiving bufter 1, the stored data
1.S
transferred to the
Receiving buffer 2 (SCBUF), and the interrupt INTRX occurs at the same
time. The CPU reads out the Receiving buffer 2 (SCBUF). Data may be
stored into the Receiving buffer 1 before the CPU reads out the
Receiving buffer
2
(SCBUF). Note, however, that an overrun occurs
unle ss the CPU reads out the Rece iving buf fer 2 (SCBUF) be fore the
Receiving buffer 1 receives all bits of
th~
next data. When an
overrun occurred, the data in the buffer 2 and
RBB
are not lost,
however, that in the buffer
1
are lost.
SeCR7
(RBB)
stores the parity bit in the case adding parity in the
B-bit UART mode and the MSB in the 9-bit UART mode.
In the 9-bit UART mode, setting SCMOD4 CWU) to "1" enables the wake-up
function of the slave controllers, and the interrupt INTRX occurs only
if
RBB=1.
@
Transmission counter
This is a 4-bit binary counter used in the asynchronous communication
(UART) mode. Like the receiving counter, it counts based on SIOCLK to
generate a transmission clock TXDCLK for every 16 counts.
SIOCLK
4 5 6 7 8 9 10 11 12 13 14 15 16 :1: 2
ill
15 16
'II
2 3
TXDCLK
l J
CD
Transmission control
1) I/O interface mode
Data in the transmission buffer are output to the TxD pin for each
bit at the rising edge of the shift clock output from the SCLK pin.
2) Asynchronous communication (UART) mode
When the CPU have written data into the transmission buffer,
transmission is started with the next rising edge of TxDCLK, and a
transmission shift clock TxDSFT is generated.
Hand-shake function
The TMP90CB40 supports a hand-shake function, by which the
connection of
crs
of one TMP90CB40 and RTS of the other TMP90CB40
allows receiving/transmitting data on a frame basis to prevent
overrun errors. This function is enabled or disabled by the control
register SCCRO (CTSE).
MPU90-117