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TOSHIBA
TMP90C840
2.
PIN ARRANGEMENT AND FUNCTIONS
The
arrangement
of
input/output
pins,
their
names
and
functions
are
described below.
2.1
Pin Arrangement
Fig. 2.1 shows where the input/output pins are located in the TMP90C840.
VREF
1
Vee
AGND
2
P37 (WAIT)
(ANO) p50
3
62
P36 (WR)
(ANI) PSI
4
P35
(RD)
(AN2) p52
5
60
P34 (CTS)
(AN3) P53
6
59
P33 (TxD)
(AN4) P54
7
P32 (TxD/RTS/SCLK)
(AN5) P55
8
P31 (RxD)
(TOI/MOO) p60
9
56
P30 (RxD)
(MOl) P61
10
55
EA
(M02) P62
11
P43 (A19)
(M03) P63
12
P42 (A18)
(T03/MIO) P70
13
P41 (Al7)
(MIl) P71
14
P40 (A16)
(Ml2) P72
15
P27
(Al~)
(Ml3) P73
16
P26 (A14)
(INTO) P80
17
P25 (A13)
(INTl/TI4) P81
18
P24 (A12)
(INT2/TIS) P82
19
P23 (All)
(T03/T04) P83
20
P22 (AIO)
NMI
21
P21 (A9)
RESET
22
P20 (AB)
CLK
23
PI7 (A7)
(DO) POO
24
P16 (A6)
(Dl) POI
25
40
PIS (AS)
(D2) P02
26
39
P14 (A4)
(D3) P03
27
P13 (A3)
(D4) P04
28
P12 (A2)
(DS) P05
29
36
Pll (AI)
(D6) P06
30
35
PIO (AO)
(D7) P07
31
X2
(GND)
Vss
32
Xl
Fig. 2.1-(1)
Pin Arrangement (Shrink Dual Inline Package)
MPU90-3
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