Toshiba TLCS-90 Series Data Book page 134

TOSHIBA nlP 8048P I ,
TMP
80 35P 1
Reading of Internal Program Memory
• The processor is placed in the READ mode by applying +12V to the EA pin and
OV
to the RESET pin. The address of the location to be read is then
applied to BUS and the low order 2-bits of Port 2. The address is latched
by a 0 to 1 transition on RESET and the high level causes the contents of
program memory location addressed to appear on the eight lines of BUS.
· Figure 7 illustrates the timing diagram for·this operation.
(5) Single Step Operation.
· A single step feature useful for debug can be implemented by utilizing a
circuit shown in Figure 8 (a) combined with the SS-pin and ALE pin.
• A D-tL£e flip flop with set and reset is used to generate
SSe
In the run
mode S5 is held high by keeping the flip flop set. To enter single step,
set is removed allowing ALE to bring
SS
low via reset input. The next
instruction is started by clocking a
"I"
into the FF which will not appear
on
SS
unless ALE is high removing reset. In response to
SS
going high
the processor begins an instruction fetch which brings ALE low resetting
FF and
causing.~~e
processor to again enter the stopped state.
The tiffiing diagram in this case is as
show~
in Figure 8 (b). (EA SV) •
• It-.e
L:)\,,-er
'IX? S:.~S
has been or ga:n
Z'::Cl
to
a:'lo;,;
po;,;er
to be removed frow all
but the volatile, 64 x 8 data R&~ array. In power down mode the contents
of data RAM can be maintained while drawing typically 10 - 15% of normal
operating power requirements .
. vee
serves as the SV supply for the bulk of the TMP8048 while the VDD
supplies only the RAM array. In standby mode
vce
is reduced to OV but VDD
is kept at 5V. Applying a low level to reset inhibits any access to the
RAN by the processor and guarantees that RA.~ cannot be inadvertently
altered as power is removed from
vce.
ss
ALE
DBD - DB7
P20 - P23
/
\
\
Address
(PC)
Address (PC)
/
Instruction Input
>-0
<
X
X
Port20 -23
Data
i
i
I
'For two
L.. _ _ _ _ _ _ _ _ _ _ ..J
instruction
Address (PC+l )
Address (PC+l)
Fig.8(b) Single Step Operation Timing
MCU48-124