Toshiba TLCS-90 Series Data Book page 232

8 bit microcontroller
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OSHrBA
6. 16-BIT ARITHHETIC
AND LOGIC OPERATIONS
I
Hnemonic
I
Bus Operation
ADD/ADC/SUB/S~CI
AND/OR/XOR/CP
HL,gg
2:N:d:d
HL,mn
2:3:N
HL.(gg)
2:R:R+1:N
HL, (ix+d) 12:d:3:R:R+1:N
I
HL. (HL+A)
2:d:d:d:d:R:R+1:NI
HL. (mn)
12:3:4:R:R+1:N
HL, (n)
2:d:R:R+1:N
ADD
iX,gg
2:N:d:d
iX,mn
2:3:N
ix, (gg)
2:R:R+1:N
ix, (jx+d) 12:d:3:R:R+1:N
I
ix, (H L + A)
2: d: d : d: d: R: R+ 1 : N
'
ix, (mn)
2:3:4:R:R+1:N
iX,(n)
2:3:R:R+1:N
IINC/DEC
rr
·N:d
1
' · ·IHc·w/D"E"C"w···fiiQ)······
··2·~·R·:··R·~·i··:·····················1
,
N: W: W+1
.
I
(ix+d)
2:d:3:R:R+1:
N:W:W+1
(HL+A)
2:d:d:d:d:R:R+1:
N:W:W+1
(mn)
2:3:4:R:R+1:
N:W:W+1
(n)
I 2: d: R: R+ 1 :
IN: W: W+1
7. ROTATES AND SHIFTS
Hnemonic
Bus Ope rat ion
RLC/RRC/RlIRRI
SLA/SRA/SLL/SRL
A
N
I
9
2:N
(gg)
2:R:N:W
I
(ix+d)
2:d:3:R:N:W
(HL+A) 12:d:d:d:d:R:N:W
(mn)
2:3:4:R:N:W
(n)
2:3:R:N:W
RLD/RRD
(gg)
2:R:d:d:N:W
(i
x+d)
2:d:3:R:d:d:N:W
(HL+A)
2:d:d:d:d:
I
R:d:d:N:W
(mn)
12:3:4:R:d:d:N:W
(n)
12:3:R:d:d:N:W
8.
BIT OPERATIONS
Mnemonic
Bus Operation
I
BIT
b,g
2:N
I
b, (gg)
2:R:N·
b, (ix+d)
2:d:3:R:N
b, (HL+A)
2:d:d:d:d:R:N
b, (mn)
\2:3:4:R:N
b, (n)
,2:d:R:N
SET/RES b,g
2:N
I
b, (gg)
2:R:N:d:W
I
b,
(·i x + d)
2 : d : 3: R: N : d : W
;
b, (HL+A)
2:d:d:d:d:
I
R:N:d:W
.
b, (mn)
12:3:4:R:N:d:W
b, (n)
12:d:R:N:d:W
i TSET
i
i
i
I
I
I
MPU90-34
b,g
2:N:d:d
b, (gg)
j 2:R:N:d:d:W
b, (ix+d) ,2:d:3:R:N:d:d:W
b, (HL+A) . 2:d:d:d:d:
b, (mn)
b,
(n)
R:N:d:d:W
2:3:4:R:N:d:d:W
2:3:R:N:d:d:W
TMP90C840

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