Toshiba TLCS-90 Series Data Book page 72

TOSHIBA
TMP80 C49AP /-6
t
TMP 80C39AP /-6, TMP 80C49AF /-6,
TMP80C49AT
t
TMP80C39AT
PIN NAMES AND PIN DESCRIPTION
VSS (p ower Supp ly)
Circuit GND potential
VCC (Power Supply)
+SV during operation
PS (Input)
PROG
P 10
P20
The control signal for the power saving at the power down mode (Active
Low)
(Output)
Output strobe for the 1'MP82C43P I/O expander.
- P 17 (Input/Output) Port 1
8-bit quasi-bidirectional port (Internal Pullup SOKn) .
- P 27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup
=
SOKn) •
P20 - P23 contain the four high order program counter bits during an external
program memory fetch and serve as a 4-bit I/O expander bus for the
TMP8243P.
DBO - DB7 (Input/Output, Tri-State)
True bidirectional port which can be written or read synchronously using
the RO, WR strobes. The port can also be statically latched. Contains
the 8 low order program counter bits during an external program memory
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data duri~ an external RAM data store inst-
ruction, under control of ALE, RO, and WR.
TO (Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
TI (Input)
Input pin testable using the JTl and JNTI instruction. Can be designated
the event counter input using the timer/STRT CNT instruction.
INT (Input)
External interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset. Also testable with conditional jump
instruction. (Active low)
RD (Output)
Output strobe activated during a Bus
onto the Bus from an external device.
Data Memory (Active Low).
WR (Output)
read. Can be used to enab Ie data
Used as a Read Strobe to External
Output strobe during a Bus write (Active Low). Used as a Write Strobe to
External Data Memory.
MCU48-62