Architecture - Toshiba TLCS-90 Series Data Book

TOSHIBA TMP90C840
3.8.2 Architecture
Fig. 3.8 (7) is a block diagram of the serial channel.
r--
Se~ial Clock Circuit--------------------j
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I
I
TRUN7. 6 T02TRG (Timer2 Comparator Output)
I
I - :
I
I
I ¢T4 :
¢T16 'SIOCLK
¢T64 :
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I
I
I
I
I
01 :
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I
I
I
I
I/O Interface :
~
_____________________
l2.0~~
_____________
J
RTS/O~----------~ r ' P - - - - - G
CTS
SCLK
~~----~
(P32)
Internal Data Bus
Fig. 3.8
(7)
Block Diagram of Serial Channel
MPU90-115
(P34)
TxD
(P32)
TxD
(P33)