Idle 1 Mode; Idle 2 Mode - Toshiba TLCS-90 Series Data Book

TOSHIBA TMP90C840
3.4.2 IDLE 1 mode
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(Level)
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Fig. 3.4 (3) illus trates the t lmlng for releas ing the HALT stat e by
interrupts in the IDLE 1 mode.
In the IDLE 1 mode, only the internal osci llator and the watchdog
timer counter operate. The system clock in the MCU stops, and the CLK
signal is fixed at the "1" level.
In the HALT state, an instruction request is sampled asynchronously
with the system clock, however the HALT release (restart of operation)
is performed synchronously with it.
(Note) An interrupt requested by the watchdog timer is prohibited
through the HALT period in this mode.
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Interrupt Acknowledge
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Fig. 3.4 (3) Timing Chart of HALT Released by
Interrupts in IDLEI Mode
3.4.3 IDLE 2 mode
Fig. 3.4 (2) shows the timing of HALT release caused by interupts in
the RUN/IDLE 2 mode.
MPU90-51