Control Registers - Toshiba TLCS-90 Series Data Book

TOSHIBA
TMP90C840
The SMC ports are controlled by three control registers (P67CR, SMMOD,
and SMCR) , and allow the selection of driving method: 1) 4-phase
I-step/2-step excitation and 2) 4-phase 1-2 step excitation.
3.7.1 Control registers
(1) Port 6 and Port 7 I/O selection register (P67CR)
This register specifies either input or output for each bit of the
4-bit I/O ports 6 and 7.
When all bits of P67CR are initialized to "0" by resetting, Ports 6
and 7 function as input ports.
P67CR is a write-only register (not for readout).
(2) Stepping motor control port mode register (SMMOD)
Ports 6 and 7 also function as SMC Ports (MO and Ml) or Timer Output
Ports (TOI and T03), as selected by SMMODl, 0 or SMMODS, 4.
When Port 6 is used as SMC Port (MO), SMMODl, 0 should be set to 10 or
II.
When Port 7 is used as SMC Port (Ml), SMMODS, 4 should be set to 10 to
make it synchronize with the trigger pulse of the timer flip-flop TFF3
and set at 11 to make it synchronize with the trigger pulse of the
Timer Flip-flop TFF4. P83 (also used as T03 and T04) can function as
T03 only when SMMODS, 4 are set at 11.
SMMOD2 and SMMOD6 serve to select the excitation method. With "0" the
full-step Cl-step/2-step) excitation is selected and with "1"
tht~
half-step (1-2 step) excitation is selected. When full-step
excitation is selected, the selection of either 1 or 2-step excitation
is determined by the initial output value.
SMMOD3 and SMMOD7 allow to set the number of phases.
(3) Stepping motor control port rotating direction control register (SMCR)
This register controls the rotating direction. The direction of the
channel 0 (MO) is set by SMCRO (CCW6) and that of the channel 1 (M1)
is set by SMCR4 (CCW7).
"a"
denotes normal rotation and "I" denotes reverse rotation.
(4) Port 6
This is a 4-bit I/O port allocated to the address FFCCH.
The lower four bits are assigned as Port 6, while the upper four bits
function as the shifter alternate register (SA6) for driving the
stepping motor with the half-step (1 - 2) excitation.
(5) Port 7
This is a 4-bit I/O port allocated to the address FFCDH.
The lower four bits are assigned as Port 7, while the upper four bits
function as the shifter alternate register (SA7) for driving the
stepping motor with the half-step (1 - 2) excitation.
MPU90-99