Toshiba TLCS-90 Series Data Book page 159

TOSHIBA
TMP 8049P I -6, TMP 8039P 1-6
If the pulse is generated externally the reset pin must be held at ground
(~0.5V)for
at least 50mS after the power supply is within tolerance •
• Reset performs the following functions within the chip:
(i)
(ii)
Sets PC to Zero.
Sets Stack Pointer to Zero.
Selects. Register Bank O.
Selects Mer.;ory Bank O.
( iii)
(iv)
(v)
(vi)
(vii)
(viii)
(ix)
(x)
(xi)
Sets BUS (DBO - DB 7) to high impedance state.
Sets Ports 1 and 2 to input mode.
(Except when EA
Disables interrupts (timer and external).
Stops Timer.
Clears Timer Flag.
Clears FO and Fl.
Disables clock output from TO.
(10) Oscillator Circuit
TMP8049 can. be operated by the external clock input in addition to
crystal oscillator as shown below.
+5V
2 XTAL 1
.----1---V
XTAL 2
lOpF
J;
2.
Basic Operation and Timing
The following basic operations and timing are explained
(1)
Instruction Cycle
(2)
External Memory Access Timing
(3)
Interface with I/O Expander TMP8243P
(4) Internal Program Verify (Read) Timing
(5) Single Step Operation Timing
(6)
Low Power Stand-by Mode
MCU48-149
XTAL 1
XTAL
2
5V)