Detection Start Timing; Detection; Table 3.1 Clock Examples - Toshiba TXZ SERIES Reference Manual

When the deviation of the reference clock frequency is ±10 % and the deviation of the target clock frequency is
±1 % (Undetected area), the setting values of [OFDMN1]<OFDMN1> and [OFDMX1]<OFDMX1> are
calculated as follows. In this example, <OFDMX1> is rounded up and <OFDMN1> is rounded down.
Detection Target Clock
Reference Clock
・Calculating formula
Register set point = (Detective target clock frequency / 4 ) / ( Standard clock frequency / 256 )
Note: The above is the example from which dividing of the reference clock is 256 dividing.
The numerical value of dividing changes with products. For detail, refer to the "Product
Information" of Reference manual.
The preset value is calculated as follows by the formula.
<OFDMX1> value = e ÷ h × 64 = 71.82 = 72 (Decimal fraction is rounded up) = 0x48
<OFDMN1> value = f ÷ g × 64 = 57.6 = 57 (Decimal fraction is rounded down) = 0x39
Then the range of the detected area is defined as follows:
a = h × <OFDMN1> ÷ 64 = 8.01 (round-down)
d = g × <OFDMX1> ÷ 64 = 12.38 (round-up)
The range of the undetected area is defined as follows:
b = g × <OFDMN1> ÷ 64 = 9.80 (round-up)
C = h × <OFDMX1> ÷ 64 = 10.12 (round-down)
That is, <OFDMX1> and <OFDMN1> are set to 0x48 and 0x39, respectively. Then, the frequency detection
reset is generated when the frequency of 12.38 MHz or more, and 8.01 MHz or less is detected.
And if the frequency of 9.80 MHz to 10.12 MHz is detected, the frequency detection reset is not generated.

3.3. Detection start timing

The time for two periods of detective periods is necessary from operation start to a detective start. During
detective operation, it is [OFDSTAT] I can confirm it in <OFDBUSY>.

3.4. Detection

The time for the two cycles of the detection cycle is required after OFD detects the abnormalities until it
generates reset. If a reset occurs, OFD will be initialized and will stop.
Note: There are multiple causes of the reset. The reset factor can be checked with the exception/interrupt
register [RLMRSTFLG1]. For the [RLMRSTFLG1] register, refer to an exception chapter in the
reference manual system.
2018-03-09

Table 3.1 Clock examples

10MHz ± 1 %
10MHz ± 10 %
= (Detective target clock frequency / Standard clock frequency ) × 64
Max 10.1 MHz
Min 9.9 MHz
Max 11.0 MHz
Min 9.0 MHz
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TXZ Family
Ocsillation Frequency Detector
---------- e
---------- f
---------- g
---------- h
Rev. 1.1