Run Mode - Toshiba TLCS-90 Series Data Book

TOSHIBA
TMP90C840
3.4.1
RUN Mode
Fig.
3.4
(2) shows the timing for releasing the HALT state by
interrupts in the RUN/IDLE 2 mode.
In the RUN mode, the system clock in the MCU continues to operate even
after a HALT instruction is executed. Only the CPU stops executing
the instruction. Until the HALT state is released, the CPU repeats
dummy cycles. In the HALT state, an interrupt request is sampled with
the r.is ing edge of the "CLK" signa
1.
Xl
...,
L.r
Lr Lr
L.r L.r Lr
Ln.1MJ1
lJ1 lJ1 Lr Lr L.r
V
~
II
~
I
1\
V
~
~
eLK
I f
-
A¢ - 19
-~
Next
~
) I
OC
Next + 1
"
I '
U
C
"
I'r-
~
J
J' ~
RD
WR
D¢ - 7
NMI
INT¢
(Level)
INT¢'1'2
(Rising Edge)
Internal INT
-
1----
---
"
I
----
~
-----1f----
~
--- ----
- - -
HALT 1nstruct10n
Execution Sequence
'c.
I I
\
{~~
JI
(C,
H
"
11"
- - - ---
1----
~
~
r.--
Interrupt Acknowlec
Sequence
Fig.
3.4
(2) Timing Chart for Releasing the HALT State by
Interrupts in RUN/IDLE 2 Modes
MPU90-S0