Toshiba TLCS-90 Series Data Book page 236

TOSHIBA TMP90C840
The overhead for the entire process from accepting an interrupt to
jumping to an interrupt processing program is 20 states.
General-Purpose
Interrupt Processing
(SP-l)
+
PCH
(SP-2)
+
peL
(SP-3)
+
A
(SP-4)
+
F
SP
+
SP-4
IFF
+
0
Fig. 3.3 (2) General Purpose Interrupt Processing Flowchart
An interrupt processing program ends with a RETI instruction.
When this instruction is executed, the data previously stacked from
the program counter PC and the register pair AF are restored.
After the CPU reads out the interrupt vector, the source of an
interrupt requested acknowledges that the CPU accepts the request, and
clears the request.
A non-maskable interrupt cannot be disabled by programming. A
maskable interrupt, on the other hand, can be enabled or disabled by
programming. An interrupt enable flip flop (IFF) is provided on the
bit 5 of Register F in the
cpu.
The interrupt is enabled or dis,abled
by setting IFF to "1" by the EI instruction or to
t'o"
by the DI
instruction, respectively. IFF is reset to "0" by the reset operation
or the acceptance of any interrupt (including non-maskable interrupt).
The EI instruction is executed after the subsecuent instructions is
executed.
MPU90-38