Toshiba TLCS-90 Series Data Book page 21

TOSHIBA TMP 8048A/TMP 80 35A, TMP 8049A/TMP 8039A
• The interrupt system is single level in that once an interrupt is
detected all further interrupt requests are ignored until execution of
an RETR (which should occur at the end of an interrupt service routine)
reenables the interrupt logic.
· An interrupt sequence is initiated by applying a low level "0" to the
INT pin.. INT is level triggered and active low which allows "Wire
Gring" of several interrupt sources. The interrupt level is sampled
every machine cycle during ALE and when detected causes a "jump to
·subroutine" at Location 3. As in any call to subroutine, the Program
Counter and Program Status Word are saved in the stack.
• When an overflow occurs in the internal timer/event counter an
interrupt request is generated which is reserviced as outlined in
previous paragraph except that a jump to Location
7
is used instead of
3. If INT and times overflow occur simultaneously then external
request
1Nf
takes precedence.
If an extra external interrupt is needed in addition to INT this can be
achieved by enabling the counter interrupt, loading FFH in the counter
(one less than the terminal count), and enabling the event counter
mode. A "1" to "0" transition on Tl will cause an interrupt vector to
Location 7.
The interrupt service routine pointed to be addresses in Location 3 or
7
must reside in memory between
a
and 2047, i.e., Bank
O.
Figure 3 illustrates the concept of the interrupt control circuit.
(6)
Stack (Stack Pointer)
• An interrupt or Call to subroutine causes the contents of the program
counter to be stored in one of the 8 register pairs of the Program
Counter Stack. The pair to be used is determined by a 3-bit stack
pointer which is part of the Program Status Words (PSW explained in
section
(8)).
Data
RAM
locations,
8
through 23 are available as stack
registers and are used to store the program counter and 4-bits of PSW
as shown in the figure.
The stack pointer when initialized points to
RAM
location
8
and
9.
The
first subroutine jump or interrupt results in the program counter con-
tents being transferred to Locations 8 and 9.
Then the stack pointer
is incremented by one to point to Locations 10 and 11. Eight levels of
subroutine are obviously possible.
· At the end of a subroutine signalled by a RET or RETR causes the stack
pointer to be decremented by one and the contents of the resulting pair
to be transferred to the Program Counter.
MCU48-11