Toshiba TLCS-90 Series Data Book page 121

TOSHIBA
TMP 8048P I , THP 80 35P I
There are three locations 1n Program Memory of special importance.
• Location 0
Address
4095
2048
2047
1024
1023
}1emory Bank 1
Memory Bank 0
Program MemoD' Area
Activating the Reset line of the processor causes the first instruc-
tion to be fetched from Location O.
• Loea: :0:-. 3
~
. . . :;: i ' \ ' " a: :. :1;
t ~.
e
i:l
t
err
u p
~
1 i ::
e c: the pro: c
S S
~!'
(:.: ::"" ..
t
e :-ru?: e:1 a :: ! e:: )
causes a ju=? to
subrou~ine define;: by ad:i::-ess h~lc in Location 3.
• Location 7
A timer/counter interrupt resulting from a timer/counter overflow
(if enabled) causes a jump to a subroutine defined by address held in
Location
7.
• Program address 0-2047 and 2048-4095 are called memory banks 0 and 1
respectively switching of memory banks is achieved by changing the
most significant bit of the program counter (PC) during execution of
an unconditional jump instruction or call instruction executed after
using SEL MBO or SEL
MBl.
Reset operation automatically selects Bank O.
(2)
Data Memory
Resident Data Memory (volatile
RAM)
is organized as
64
words by 8-bits
wide •
. The first 8 locations
(0 -7)
of the memory array are designated as
working registers and are directly addressable by several
instructions. By executing a Register Bank switch instruction (SEL
RBI)
locations 24 - 31 are designated as the working registers in
place of
0 - 7.
MCU48-l11