Toshiba TLCS-90 Series Data Book page 30

TOSHIBA TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
Reading of Internal Program Memory
The processor is placed in the READ mode by applying +12V to the EA pin
and OV to the RESET pin. The address of the location to be read is
then applied to BUS and the low order 2 or 3 bits of Port 2. The
address is latched by a 0 to 1 transition on RESET and the high level
causes the contents of program memory location addressed to appear on
the eight lines of BUS.
Figure 7 illustrates the timing diagram for this operation.
(5) Single Step Operation.
• A single step feature useful for debug can be implemented by utilizing
a circuit shown in Figure 8 (a) combined with the 5S pin and ALE pin.
• A D-type flip flop with set and reset is used to generate 55. In the
run mode
S:S
is held high by keeping the fIiE-flop set. To enter single
step, set is removed allowing ALE to bring 55 low via reset input. The
next instruction is started by clocking a "1" into the FF which will
not appear on 55 unless ALE is high removing reset. In response to 5S
going high the processor begins an instruction fetch which brings ALE
low resetting FF and causing the processor to again enter the stopped
state.
• The timing diagram in this case is as shown in Figure 8 (b). (EA=5V)
(6) Lower Power Stand-by Mode
• The Lower TMP8048A has been organized to allow power to be removed from
all but the volatile, 64 x 8 or 128 x 8 data RAM array. In power down
mode the contents of data ruu~ can be maintained while drawing typically
10 - 15% of normal operating power requirements.
· vee
serves as the 5V supply for the bulk of the TMP8048A while the VDD
supplies only the RAM array. In standby mode
vee
is reduced to OV but
VDD is kept at 5V. Applying a low level to reset inhibits any access
to the RAM by the processor and guarantees that ~~ cannot be inadver-
tently altered as power is removed from
vee.
ss
ALE
DBO - DB7
P20-P23
I \
\
Address (PC)
Address (PC)
/
Instruction Input
>-0
<
X
X
Port20 - 23
Data
i
i
I I
For two '-----------.j
lnst ruct ion
Address (PC+l)
Address (pC+l)
Fig. 8(b) Single Step Operation Timing
MCU48-20