Toshiba TLCS-90 Series Data Book page 45

TOSHIBA
TMP 80 C48AP / -6, TMP 80 C35 AP / -6, TMP 80 C48AF / -6,
TMP80C48AT,TMP80C35AT
8-BIT SINGLE-CHIP MICROCOMPUTER
TMPBOC48AP /TMP80C48AP-6
TMP80C35AP /TMP80C35AP-6
TMP80C48AF/TMP80C48AF-6
TMP80C48AT/TMP80C35AT
GENERAL DESCRIPTION
The TMP 80 C48A is a single chip mi crocomputer fabri ca ted in Si
1
i con Gat e Q10S
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been included
in a single chip; an 8-bit CPU, 64 x 8 RAM data memory, lK x 8 ROM program
memory, 27 I/O lines and an 8-bit timer/event counter.
The TMP80C48A is particularly efficient as a controller. It has extensive bit
handling capability as well as facilities for both binary and BCD arithmetic.
The TMP80C35A/-6 is the equivalent of a TMP80C48A/-6 without ROM program
memory on chip. By using this device with external EPROM or RAM, software
debugging becomes easy.
The TMP80C48AP/-6 and TMP80C35AP/-6 are 1n a standard Dual Inline Package.
The TMP80C48AF/-6 is in a 44-pin Flat Package.
The TMP80C48AT and TMP80C35AT are
packag~d
in the JEDEC standard type 44pin
PLCC
(p
las t ic Leaded Ch ip Carrier)
FEATURES
.TMP80C48AP/TMP80C35AP/TMP80C48AF/
TMP80C48AT/TMP80C35AT
l.36~s Instruction Cycle Time
O·C to 70·C, 5V
±
10%
• TMP80C48AP-6/TMP 80C3SAP -6/TMP 80 C48AF-6
2.S
~s
Instruction Cycle Time
-40·C to 8S·C, SV
±
20%
• Software Upward Compatible with
TMP8048AP/INTEL's 8048
• HALT Instruction (Additional Instruction)
• lK x 8 masked ROM
.64x8RAM
• 27 I/O lines
• Interval Timer/Event Counter
MCU48-3S
• Low Power
lOrnA MAX. in Normal Operation
(VCC=SV, fXTAL=6MHz)
lO~A Max. in Power Down Mode
(VCC=SV, fXTAL : DC)
• Single Power Supply
• Power Down Mode (Stand-by Mode)
• Halt Mode (Idle Mode)