Toshiba TLCS-90 Series Data Book page 274

TOSHIBA TMP90C840
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Up-counter
This is an 8-bit binary counter that counts up by an input clock pulse
specified by an 8-bit timer clock control register (TCLK) and an 8-bit
timer mode register (TMOD).
The input clock pulse for Timer
a
and 2 is selected from
~T1, ~T16
and
~T256
according to the setting of the TCLK register.
However,
~T256
cannot be selected as the input clock pulse for these
timers in the 16-bit timer mode (TMOD3,2=Ol/TMOD7,6=01).
Example: When setting TCLKl,
a
"01", s6Tl is selected as the input
clock pulse for Timer
o.
The input clock pulse to Timer 1 and 3 is selected according to the
operating mode. In the 16-bit timer mode, the overflow output of
Timer 0 and 2 is automatically selected, regardless of the setting of
the TCLK register.
In the other operating modes, the clock pulse is selected among the
internal clocks s6T1,
~T16
and ¢T256, and the output of the Timer 0 and
2 comparator (match signal).
Example: If TMOD3,2 = 01, the overflow output of Timer 0 is selected
as the input clock to Timer 1.
If TMOD3,2 = 00 and TCLK3,2 = 01, ~Tl is selected as the
input clock to Timer 1.
The operating mode is selected by the TMOD register. This register is
initia 1 ized to TMOD3, 2 =OO/TMOD7 ,6=00 by resett ing, where by the
up-counter is placed in the 8-bit timer mode.
The up-counter can control its functions, count, stop or clear, for
each interval timer as selected by the timer control register TRUN.
By resetting, all up-counters are cleared to stop the timers.
MPU90-76