Operation - Toshiba TLCS-90 Series Data Book

TOSHIBA
TMP90C840
Data write timing
--fLs\
If
I
~\
C""'"
jStopped
H
Transmission
13 14 16 1 2
14 15 16
1
2
3
SIOCLK
T
--.,
I
I
TXDCLK
""""5
n
H
n
TxD
--.,]
\start bit
A
bit 0
51
(Note)
1)
Keep the CTS signal at the "H" level until data are written into
the transmission buffer (SCBUF).
A fa 11 of the CTS signa 1 halts the transmis ison
0
f the next
data.
2)
The transmission is restarted from the first fall of TXDCLK
after a fall of the CTS signal.
Fig. 3.8 (10) Hand-shake by CTS (clear to send) Signal
QD
Transmission buffer
The transmission buffer (SCBUF) shifts out the data written by the CPU
from the LSB as based on the shift clock TXDSFT generated by the
transmission control unit. When all bits are shifted out, the
transmission buffer becomes empty, generating the interrupt INTTX.
GD
Parity control circuit
3.8.3
(1)
Setting the serial channel control register SCCRS (PE: Parity enable)
to "1" allows the addition of a parity bit in transmitting/receiving
data, only in the 7-bit DART or 8-bit DART mode. Either even or odd
parity can be selected by the SCCR6 (EVEN) register.
In the transmission mode, the parity is automatically generated as
based on the data written into the transmission buffer (SCBUF),
storing into the 7th bit (TB7) of SCBUF in the 7-bit DART mode or into
TB8 in the 8-bit DART mode for transmission. PE and EVEN should be
designated before writing data into the transmission buffer.
In the receiving mode, the parity is generated from data shifted into
the receiving buffer 1 and transferred to the receiving buffer
2
(SCBUF). A parity error is detected and the PERR flag is set if the
parity status mismatches the 7th bit (RB7) of'SCBOF in the 7-bit DART
mode or RB8 in the 8-bit DART mode.
Operation
Mode 0 (I/O interface mode)
This mode is used to increase the number of I/O pins of the TMP90C840
for transmitting/receiving data and supplying a synchronous clock
(SCLK) to an external shift register.
MPU90-1l9