User Dip Switch - Xilinx SP605 User Manual

User DIP Switch

The SP605 includes an active-High four-pole DIP switch, as described in
Table
pulled up to 1.5V, when closed.
X-Ref Target - Figure 1-17
Table 1-25: User DIP Switch Connections
SP605 Hardware User Guide
UG526 (v1.1.1) February 1, 2010
1-25. Three poles (switches 1-3) are pulled up to 2.5V, and one pole (switch 4) is
VCC1V5_FPGA
VCC2V5
S2
5
6
7
8
SDMX-4-X
Figure 1-17: User DIP Switch S2
U1 FPGA Pin
C18
Y6
W6
E4
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4
3
2
1
2 2
1 1 1
Schematic Net Name
GPIO_SWITCH_0
GPIO_SWITCH_1
GPIO_SWITCH_2
GPIO_SWITCH_3
Detailed Description
Figure 1-17
GPIO_SWITCH_3
GPIO_SWITCH_2
GPIO_SWITCH_1
GPIO_SWITCH_0
2 2
1
UG526_17 _102609
DIP Switch Pin
S2.1
S2.2
S2.3
S2.4
and
43