Block Diagram - Hitachi HD64411 Q2 User Manual

CLK0
CPG0
Rendering unit
Rendering
Address
buffer unit
control
(22)
SuperH
∆YUV>>RGB
DMA control
CPU-I/F
Data
(16)
1 . 2

Block Diagram

Figure 1-2 shows a block diagram of the Q2. The functions of the various blocks in figure 1-2 are
as follows.
• Rendering unit
Performs fetching and interpretation of the display list on the UGM, references the source data
on the UGM, and output drawing data to the drawing-side frame buffer on the UGM.
• Rendering buffer unit
Buffers data and addresses between the rendering unit and the UGM, and outputs them
efficiently.
• CPU interface unit
Performs control relating to connection to the CPU bus.
• Memory interface unit
Performs control relating to connection to the UGM bus.
• Display unit
Controls the control signals sent to the CRT device.
2
Quick 2D graphics renderer
CLKi
CPG1
Display unit
RGB >> YCrCb
Display buffer
unit
Color palette
Chip UGM
manager I/F
Address (16)
EDO-DRAM: 4 M to 32 M
UGM (unified graphics memory)
Frame buffer 0 Frame buffer 1
Binary/multi-valued
Binary work area
source
Display list
Figure 1-1 Overview of Q2 System
CLK0
DCLK
SYNC
R: 6
D/A
G: 6
D/A
B: 6
D/A
16 bits
(YCrCb: 8, 8/8 bits)
MIX
Data (16)
External video
NTSC
Digital video
encoder