Table of Contents
Advertisement
Bit 9—Display Area Change (DC): Controls frame buffer switching in manual display
change mode.
Bit 9:
D C
Description
0
Switching of the frame buffer for display is not performed in manual display change
mode.
1
Switching of the frame buffer for display is performed in manual display change mode.
Switching is performed in frame units in non-interlace and interlace modes, and in field
units in interlace sync & video mode.
This bit is cleared to 0 after frame buffer switching.
Bit 8—Rendering Start (RS): Specifies the start of rendering.
Bit 8
R S
Description
0
Rendering is not started.
1
Rendering is started. This bit is cleared to 0 after rendering starts.
When starting rendering, have a UGM dummy read performed by the CPU, clear the
internal FIFO, and then set this bit to 1. The internal FIFO is cleared automatically 64
CLK0 cycles later, after which drawing can be performed by setting this bit to 1.
Bits 7 and 6—Double-Buffer Mode 1 and 0 (DBM1, DBM0): These bits select
double-buffer control.
Bit 7:
Bit 6:
DBM1
DBM0
0
0
1
1
0
1
Description
Auto display change mode is set.
Auto rendering mode is set.
Manual display change mode is set.
Setting prohibited
(Initial value)
(Initial value)
129
Advertisement
Table of Contents
