Memory Mode Register (Memr) - Hitachi HD64411 Q2 User Manual

Bit 9—Command Suspend Flag Enable (CSE): Enables or disables interrupts initiated
by the CSF flag in SR.
Bit 9:
C S E Description
0 Interrupts initiated by the CSF flag in SR are disabled.
Interrupts initiated by the CSF flag in SR are enabled. When CSF·CSE = 1, an IRL
1
interrupt request is sent to the CPU.
Bits 8 to 0—Reserved: Only 0 should be written to these bits.
5 . 3 . 5

Memory Mode Register (MEMR)

Bit: 15 14
— —
— —
Initial value:
Read/Write: — —
Note: * Value is retained.
The memory mode register (MEMR) is a 16-bit readable/writable register that specifies the size of
UGM used and the number of row addresses.
If the value of this register is modified during a memory access, operation will be temporarily
unstable.
MEMR bits MES2 to MES0, MEA1, and MEA0 retain their values in a reset.
Bits 15 to 7—Reserved: Only 0 should be written to these bits.
Bits 6 to 4—Memory Size (MES2 to MES0): These bits select the size and quantity of
memories used for the UGM.
Bit 6: Bit 5:
M E S 2 M E S 1
0 0
1
1 *
*: Don't care
13 12 11 10 9
— — — — —
— — — —
—
— — — — —
Bit 4:
M E S 0 Description
Memory size: 4 Mbits × 1
0
Memory size: 4 Mbits × 2
1
Memory size: 16 Mbits × 1
0
Memory size: 16 Mbits × 2
1
* Setting prohibited
8 7 6 5 4
— — MES2 MES1 MES0
— * * *
—
— — R/W R/W R/W
(Initial value)
3 2 1 0
MEA1 MEA0 — —
* * — —
R/W R/W — —
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