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HSYNC
Figure 5-1 (b)
External Update Interval (Interlace Mode and Interlace Sync &
Internal Updating: Some address-mapped registers have an internal update function. The
internal update function is provided to prevent display flicker when the CPU modifies address-
mapped registers relating to display operations without being aware of the display timing.
The display controller references address-mapped registers in coordination with display timing, and
latches data in an internal register. This data transfer is called internal updating. Internal updating is
carried out while the DRES is set to 1 in the system control register (SYSR) and at the beginning
of each frame. The update is performed on setting of the fall of VSYNC when TVM1 = 0 and
TVM0 = 0 in the display mode register (DSMR) (master mode), and on detection of the fall of
EXVSYNC when TVM1 = 1 and TVM0 = 0 (TV mode). Internal updating is not performed when
TVM1 = 0 and TVM0 = 1.
The address-mapped registers provided with the internal update function are shown in tables 5-7 (a)
and (b). The initial values of these registers should be set while the DRES bit is set to 1.
However, internal updating is performed for display start address 0 and display start address 1 in
display operations. In drawing operations, external updating is used.
Display area
External update interval
Display area
External update interval
Video Mode)
VBK and FRM flags
both set to 1
Only VBK flag
set to 1
125
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