Table of Contents
Advertisement
Bits 7 and 6—TV Sync Mode (TVM1, TVM0): These bits specify TV sync mode, in
which synchronous operation is performed by means of HSYNC and VSYNC input from an
external source, or master mode, in which HSYNC and VSYNC are output.
Bit 7:
Bit 6:
T V M 1
T V M 0
0
0
1
1
0
1
Bits 5 and 4—Scan Mode (SCM1, SCM0): These bits specify the display output scan
mode and the unit of display switching.
Bit 7:
Bit 6:
T V M 1
T V M 0
0
0
1
1
0
1
140
Description
Master mode is set. The Q2 outputs HSYNC, VSYNC , and ODDF signals.
Synchronization system switching mode is set. Switching is performed
from TV sync mode to master mode, or vice versa, via this mode.
In this mode, display operations are forcibly halted and the DISP pin
output goes low. The clock supply to the CLK1 pin can also be stopped
(input invalidated) (fixed high within the chip).
The HSYNC, VSYNC , and ODDF pins are inputs.
TV sync mode is set. HSYNC, VSYNC , and ODDF signals are input to the
Q2.
Setting prohibited
Description
Non-interlace mode: Frame buffer switching can be performed in 1-VC
units.
Setting prohibited
Interlace mode: Frame buffer switching can be performed in 2-VC units.
Interlace sync & video mode: Frame buffer switching can be performed in
1-VC units.
(Initial value)
Advertisement
Table of Contents
