Hitachi HD64411 Q2 User Manual page 57

Quick 2d graphics renderer
Table of Contents

Advertisement

Screen Display: In the Q2, the DEN (display enable) bit in the system control register (SYSR)
can be used to select whether or not display data is to be output to the screen. When display data is
not output, the display off output register (DOOR) settings are displayed.
The frame flag (FRM) and vertical blanking flag (VBK) in the status register indicate the position
of the fall of the vertical sync signal (VSYNC) determined by the set value (VSP9–0) in the
vertical sync position register (VSPR) regardless of the synchronization method.
Scanning Systems: The Q2 allows selection of non-interlace mode, interlace sync mode, or
interlace sync & video mode as the scanning system. The mode setting is made in the SCM (scan
mode) bits in the display mode register (DSMR). In non-interlace mode, one frame is composed of
one field. In interlace sync mode, one frame is composed of two fields, even and odd, in which the
same data is displayed. In interlace sync & video mode, also, one frame is composed of two fields,
even and odd, but in this mode different data is displayed in these two fields. In master mode, the
Q2 outputs a high-level signal from the ODDF pin during even field display, and a low-level
signal during odd field display. In TV sync mode, a high-level signal is input at the ODDF pin to
display the even field, and a low-level signal to display the odd field. Figure 3-15 shows examples
of raster scan control display.
50

Advertisement

Table of Contents
loading

Table of Contents