Notes On Data Transfer In Yuv Mode; Software Reset Bit - Hitachi HD64411 Q2 User Manual

6 . 3

Notes on Data Transfer in YUV Mode

1. If data transfer is performed continuously by CPU access when a YUV mode setting of 10 (∆
YUV-RGB conversion) is used, provide for an interval of 36 CLK0 cycles or more to be left
immediately before transferring the last data of each raster.
2. If data transfer is performed continuously by CPU access when a YUV mode setting of 01
(YUV-RGB conversion) is used, leave an interval of 36 CLK0 cycles or more at the start of a
line, and then when data is set in the image data entry setting register, perform a dummy read of
the Q2's status register only after setting odd-numbered data. The figure 6-3 shows the transfer
procedure for one line.
Wait of 36
CLK0 or more
1st
setting
Figure 6-3
3. When YUV mode = 01 or 10 , do not perform reads of the registers shown in the table below.
A [ 1 0 : 1 ] Register Abbreviation
007 IEMR
010 DMASHR
011 DMASLR
012 DMAWR
021 ISAHR
022 ISALR
023 IDSXR
024 IDSYR
025 IDER
026–0FF —
4. When YUV mode = 01 and DMA mode = 11, data transfer to the Q2 cannot be performed by
the DMA controller.
6 . 4

Software Reset Bit

If the software reset bit (bit 15) in the system control register is set to 1 when the Q2 is
performing drawing operations, the display address may cease to be updated. Therefore, the software
164
Dummy 2nd 3rd
read setting setting
Data Transfer Procedure for One Line
Register Name
Input data conversion mode
DMA transfer start address
DMA transfer start address
DMA transfer word count
Image data transfer start address
Image data transfer start address
Image data size
Image data size
Image data entry
Reserved
Dummy 4th 5th
read setting setting
Dummy
read