Status Register Clear Register (Srcr) - Hitachi HD64411 Q2 User Manual

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Status Register Clear Register (SRCR)

Bit: 15 14
TVCL FRCL
Initial value: * *
Read/Write: W W
Note: * Value is retained.
The status register clear register (SRCR) is a 16-bit write-only register that clears the
corresponding flags in SR. Writing 1 to one of bits 15 to 9 in SRCR will clear the corresponding
flag in SR to 0. When SR clearing is completed, the value of SRCR is cleared to all-0 internally
(a read will return 0).
B i t Bit Name
15 TV sync signal error flag clear
14 Frame buffer clear
13 DMA flag clear
12 Command error flag clear
11 Vertical blanking flag clear
10 Trap flag clear
9 Command suspend flag clear
8–0 Reserved
134
13 12 11 10 9
DMCL CECL VBCL TRCL CSCL
* * * * *
W W W W W
Abbreviation Description
TVCL
FRCL
DMCL
CECL
VBCL
TRCL
CSCL
—
8 7 6 5 4
— — — —
—
— — — — —
— — — — —
Writing 1 to the TVCL bit clears the
TVR flag to 0 in SR.
Writing 1 to the FRCL bit clears the
FRM flag to 0 in SR.
Writing 1 to the DMCL bit clears the
DMF flag to 0 in SR.
Writing 1 to the CECL bit clears the
CER flag to 0 in SR.
Writing 1 to the VBCL bit clears the
VBK flag to 0 in SR.
Writing 1 to the TRCL bit clears the
TRA flag to 0 in SR.
Writing 1 to the CSCL bit clears the
CSF flag to 0 in SR.
Only 0 should be written to these
bits.
3 2 1 0
— — — —
— — — —
— — — —