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6 . 8
Power-On Sequence
The CLK0, CLK1, and RESET signal timing when powering on is shown in the figure 6-4. The
time from the rise of VCCn until the rise of CLK0 and CLK1 should be 100 ms or less, and the
time from the rise of VCCn until the rise of RESET, 100 ms or more. If CLK0 and CLK1 are
stopped for a long period (100 ms or more) after powering on, the chip may be damaged.
4.5 V
1.5 V
VCCn
Max. 100 ms
Min. 0 ms
CPU VCCn
3.6 V
CLK0, CLK1
Min. 100 ms
0.8 V
RESET
Figure 6-4
CLK0, CLK1, RESET Signal Timing
167
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