Horizontal Sync Pulse Width Register (Hswr); Horizontal Scan Cycle Register (Hcr) - Hitachi HD64411 Q2 User Manual

Bits 15 to 9 of DSWR (HDS) and DSWR (VDS) and bits 15 to 10 of DSWR (HDE) and DSWR
(VDE) are reserved. Only 0 should be written to these bits (a read will return an undefined value).
DSWR (HDS/HDE/VDS/VDE) bits HDS, HDE, VDS, and VDE retain their values in a reset.
5 . 5 . 2

Horizontal Sync Pulse Width Register (HSWR)

Bit: 15 14
— —
Initial value: — —
Read/Write: — —
Note: * Value is retained.
The horizontal sync pulse width register (HSWR) is a 16-bit readable/writable register that
specifies the horizontal signal low-level pulse width in dot-clock units.
Bits 15 to 17 of HSWR are reserved. Only 0 should be written to these bits (a read will return an
undefined value).
HSWR bits HSW retain their values in a reset.
5 . 5 . 3

Horizontal Scan Cycle Register (HCR)

Bit: 15 14
— —
Initial value: — —
Read/Write: — —
Note: * Value is retained.
The horizontal scan cycle register (HCR) is a 16-bit readable/writable register that specifies the
horizontal scan cycle in dot-clock units. In TV sync mode (bits TVM1 and TVM0 set to 10 in
DSMR), this register setting must be made so that the HSYNC cycle specified by this register is
the same as or greater than the EXHSYNC cycle.
Bits 15 to 11 of HCR are reserved. Only 0 should be written to these bits (a read will return an
undefined value).
HCR bits HC retain their values in a reset.
13 12 11 10 9
— — — — —
— — — — —
— — — — —
13 12 11 10 9
— — — HC HC
— — — * *
— — — R/W R/W
8 7 6 5 4
— — HSW HSW HSW
— — * * *
— — R/W R/W R/W
8 7 6 5 4
HC HC HC HC HC
* * * * *
R/W R/W R/W R/W R/W
3 2 1 0
HSW HSW HSW HSW
* * * *
R/W R/W R/W R/W
3 2 0
1
HC HC HC HC
* * * *
R/W R/W R/W R/W
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