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Bit 13—DMA Flag Enable (DME): Enables or disables interrupts initiated by the DMF
flag in SR.
Bit 13:
D M E
Description
0
Interrupts initiated by the DMF flag in SR are disabled.
Interrupts initiated by the DMF flag in SR are enabled. When DMF·DME = 1, an IRL
1
interrupt request is sent to the CPU.
Bit 12—Command Error Flag Enable (CEE): Enables or disables interrupts initiated by
the CER flag in SR.
Bit 12:
C E E
Description
0
Interrupts initiated by the CER flag in SR are disabled.
Interrupts initiated by the CER flag in SR are enabled. When CER·CEE = 1, an IRL
1
interrupt request is sent to the CPU.
Bit 11—Vertical Blanking Flag Enable (VBE): Enables or disables interrupts initiated
by the VBK flag in SR.
Bit 11:
V B E
Description
0
Interrupts initiated by the VBK flag in SR are disabled.
Interrupts initiated by the VBK flag in SR are enabled. When VBK·VBE = 1, an IRL
1
interrupt request is sent to the CPU.
Bit 10—Trap Flag Enable (TRE): Enables or disables interrupts initiated by the TRA flag
in SR.
Bit 10:
T R E
Description
0
Interrupts initiated by the TRA flag in SR are disabled.
Interrupts initiated by the TRA flag in SR are enabled. When TRA·TRE = 1, an IRL
1
interrupt request is sent to the CPU.
136
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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