Interface Control Registers; System Control Register (Sysr) - Hitachi HD64411 Q2 User Manual

5 . 3

Interface Control Registers

The interface control registers comprise eight 16-bit registers related to overall Q2 control, mapped
onto addresses (A10–A1) H'000 to H'007.
5 . 3 . 1

System Control Register (SYSR)

15 14
Bit:
SRES DRES
Initial value: 1 1
Read/Write: R/W R/W
Note: * Value is retained.
The system control register (SYSR) is a 16-bit readable/writable register that specifies Q2 system
operation.
SYSR is initialized as follows in a reset:
• Bits SRES and DRES are set to 1.
• Bits DEN, RS, DMA1, and DMA0 are cleared to 0.
• Bits DBM1 and DBM0 retain their values.
Bit 15—Software Reset (SRES): Controls execution and suspension of command
processing,
Bit 15:
S R E S Description
0 Command processing execution is enabled.
1 SRES is set to 1 when a hardware reset is performed. Clear SRES to 0 in initialization.
Set SRES to 1 with software.
Bit 14—Display Reset (DRES)
13 12
11 10 9
DEN — — — DC
0 — — — 0
R/W — — — R/W
6 5 4
8 7
RS DBM1 DBM0 DMA1 DMA0
0 * * 0 0
R/W R/W R/W R/W R/W
3 2 1 0
— — — —
* * * *
R/W R/W R/W R/W
(Initial value)
127