5 . 5
Display Control Registers
The display control registers comprise twelve 16-bit registers for setting the display timing,
mapped onto addresses (A10–A1) H'013 to H'01E.
5 . 5 . 1
Display Window Registers (DSWR (HDS/HDE/VDS/VDE))
Bit:
15
14
DSWR (HDS)
—
—
Initial value:
—
—
—
Read/Write:
—
Bit:
15
14
DSWR (HDE)
—
—
Initial value:
—
—
—
—
Read/Write:
Bit:
15
14
DSWR (VDS)
—
—
Initial value:
—
—
Read/Write:
—
—
Bit:
15
14
DSWR (VDE)
—
—
Initial value:
—
—
—
—
Read/Write:
Note: * Value is retained.
The display window registers (DSWR (HDS/HDE/VDS/VDE)) are 16-bit readable/writable
registers that specify the horizontal and vertical output timing for the display screen.
1. Horizontal Display Start Position (Bits HDS): Field that specifies the horizontal display start
position in dot-clock units.
2. Horizontal Display End Position (Bits HDE): Field that specifies the horizontal display end
position in dot-clock units.
3. Vertical Display Start Position (Bits VDS): Field that specifies the vertical display start
position in dot-clock units.
4. Vertical Display End Position (Bits VDE): Field that specifies the vertical display end position
in dot-clock units.
150
13
12
11
10
9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
12
11
10
9
—
—
—
—
HDE
—
—
—
—
*
—
—
—
—
R/W
13
12
11
10
9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
12
11
10
9
—
—
—
—
VDE
—
—
—
—
*
—
—
—
—
R/W
8
7
6
5
4
HDS
HDS
HDS
HDS
HDS
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
8
7
6
5
4
HDE
HDE
HDE
HDE
HDE
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
8
7
6
5
4
VDS
VDS
VDS
VDS
VDS
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
8
7
6
5
4
VDE
VDE
VDE
VDE
VDE
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
3
2
1
0
HDS
HDS
HDS
HDS
*
*
*
*
R/W
R/W
R/W
R/W
3
2
1
0
HDE
HDE
HDE
HDE
*
*
*
*
R/W
R/W
R/W
R/W
3
2
1
0
VDS
VDS
VDS
VDS
*
*
*
*
R/W
R/W
R/W
R/W
3
2
1
0
VDE
VDE
VDE
VDE
*
*
*
*
R/W
R/W
R/W
R/W