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2 . 3
CPU Interface Pins
2 . 3 . 1
CPU Writes
The CPU can access the UGM or Q2 internal registers. In a UGM access, a low-level signal is
input to CS0; in a Q2 internal register access, a low-level signal is input to CS1. CS0 and CS1
should not be driven low at the same time. The UGM or Q2 internal register address is input to A1
to A22. The address is a word address. Only word (2-byte) access can be used with the Q2. Input a
low-level signal to either WE0 or WE1 , or to both. If the CPU is an SH7040 or SH7042, the
WAIT pin is also used as A20, and therefore the UGM capacity is limited. The allocation of
ROM, etc., in the memory space must be taken into consideration when determining the UGM
capacity.
The Q2 uses an asynchronous interface for the CPU interface, and a delay in a CPU access due to a
Q2 source is reported to the CPU by means of the WAIT signal. However, the high-level width
specification for the WE0 and WE1 signals must be observed. Therefore, if the CPU is an SH-1 or
SH-2, either turn Q2 multiplication off and input the clock output from the CK pin directly to the
Q2's CLK0 pin so that the CPU and Q2 operate on clocks with the same frequency and the same
phase (clock-synchronous interface), or, when the Q2 multiplication factor is N, input a clock to
the CLK0 pin such that the N × CLK0 frequency is higher than that of the clock output from the
CK pin, so that the Q2's WE0 , WE1, and RD signal high-level width specifications are satisfied
(clock-asynchronous interface). See Section 6, Usage Notes, for detailed information concerning
clocks. If the CPU is an SH-3, the clock output from the CK pin cannot be input directly to the
Q2's CLK0 pin, because the signal output from the CK pin is a 3.3 V TTL interface signal, while
the Q2's CLK0 pin signal is a 5 V CMOS interface signal.
To enable the SuperH to recognize the WAIT signal output by the Q2, enable SuperH hardware
waits and set a software cycle. The software cycle is determined by the relationship between the
frequency of the clock output from the CK pin and the frequency of the clock input to the CLK0
pin. For examples of software wait specification, see the HD64411 Q2 Application Note. When an
SH704X is used, a setting must be made to extend the CS assertion period. Byte access to registers
must not be used since this will corrupt the accessed register or UGM data.
20
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