Rendering Control Registers; Command Status Registers H And L (Cstrh, Cstrl) - Hitachi HD64411 Q2 User Manual

5 . 6

Rendering Control Registers

The rendering control registers comprise two 16-bit registers related to rendering control, mapped
onto addresses (A10–A1) H'01F and H'020.
5 . 6 . 1

Command Status Registers H and L (CSTRH, CSTRL)

Bit: 15 14
CSTRH — —
Initial value: — —
Read/Write: — —
Bit: 15 14
CSTRL
Initial value: * *
R R
Read/Write:
Note: * Value is retained.
Command status registers H and L (CSTRH, CSTRL) are 16-bit read-only registers that store the
address of the command word (op code word) being executed when frame switching is performed.
The upper bits (A22 to A16) of the command word address are indicated by the CSTH field, and the
lower bits (A15 to A1) by the CSTL field. The address indicated by the CSTH and CSTL fields is
a word address.
Bits 15 to 7 of CSTRH and bit 0 of CSTRL are reserved. These bits always read 0.
The CSTH field in CSTRH and the CSTL field in CSTRL retain their values in a reset.
13 12 11 10 9
— — — — —
— — — — —
— — — — —
13 12 11 10 9
CSTL (address A15–A1 setting)
* * * * *
R R
R R R
8 7 6 5 4
— — CSTH (address A22–A16 setting)
— — * * *
— —
R R R
8 7 6 5 4
* * * * *
R R R R R
3 2 1 0
* * * *
R R R R
3 2 1 0
—
* * * —
R R R —
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