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Bits 3 and 2—Memory Address Mode (MEA1, MEA0): These bits select the number
of row addresses for the memory used for the UGM.
Bit 6:
Bit 4:
M E S 2
M E S 0
0
0
1
1
0
1
Bits 1 and 0—Reserved: Only 0 should be written to these bits.
5 . 3 . 6
Display Mode Register (DSMR)
Bit:
15
14
—
—
Initial value:
—
—
Read/Write:
—
—
Note: * Value is retained.
The display mode register (DSMR) is a 16-bit readable/writable register that specifies the Q2
display operation.
If the value of this register is modified during a display operation, operation will be temporarily
unstable.
DSMR is initialized as follows in a reset:
Bit YCM is initialized to 0, bits TVM1 and TVM0 to 10, and bits REF3 to REF0 to 1000.
The DOT, SCM1, and SCM0 bits retain their values.
Bits 15 to 10—Reserved: Only 0 should be written to these bits.
Bit 9—RGB-YC Conversion (YCM): Specifies YC conversion when display data is to be
output in YC mode.
Bit 9:
Y C M
Description
0
RGB-YC conversion is not performed.
1
RGB-YC conversion is performed.
138
Description
9 row addresses
10 row addresses
11 row addresses
12 row addresses
13
12
11
10
9
—
—
—
—
YCM
—
—
—
—
0
—
—
—
—
R/W
8
7
6
5
4
DOT
TVM1
TVM0
SCM1
SCM0
*
1
0
*
*
R/W
R/W
R/W
R/W
R/W
3
2
1
0
REF3
REF2
REF1
REF0
1
0
0
0
R/W
R/W
R/W
R/W
(Initial value)
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