Hitachi HD64411 Q2 User Manual page 190

(5) DMA Write Cycle
Table 7-8 DMA Write Cycle
I t e m
RD "High" Level Setup Time t
RD "High" Level Width
RD "High" Level Hold Time
RD "Low" Level Width
Write Data Hold Time
Write Data Turn Off Time
Write Data Setup Time For
RD
DREQ Delay Time
DREQ Negate Time
DACK Setup Time
DACK Hold Time
Notes: 1. If the fall of DACK is later than the fall of RD , the specification of t
DACK .
2. If the rise of DACK is earlier than the rise of RD , the specifications of t
t , and t
WRDOF WRDRS
(6) Interrupt Output
Table 7-9 Interrupt Output
I t e m
IRL Delay Time
IRL "Low" Level Width
Symbol Min M a x
1/2 ×
—
RDS
t – 9
cyc0
t t —
RDHW cyc0
12 – 1/2 ×
t —
RDH
t
cyc0
t 3t —
RDLW cyc0
t 0 —
WRDH
t — 30
WRDOF
t 2t —
WRDRS cyc0
t — 25
DAD
t — 3t
DAN
t 0 —
DAS
t 0 —
DAH
are from the rise of DACK .
Symbol Min M a x
t — 25
IRD
t 2t —
IRLW cyc0
T e s t
Unit Conditions N o t e s
ns Figure 7-8
Figure 7-9
ns
ns
ns
ns
ns
ns
ns
ns
cyc0
ns
ns
RDLW
T e s t
Unit Conditions N o t e s
ns Figure 7-10
ns
Multiplica-
tion off
Multiplica-
tion off
1
2
is from the fall of
, t ,
RDLW WRDH
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