Input Data Conversion Mode Register (Iemr) - Hitachi HD64411 Q2 User Manual

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Input Data Conversion Mode Register (IEMR)

ÉrÉbÉg 15 14 13
— —
—
èâä˙íl — — —
R/W — — —
Note: * Value is retained.
The input data conversion mode register (IEMR) is a 16-bit readable/writable register that specifies
the conversion format for input data from the CPU.
If the value of this register is modified during a data conversion, operation will be temporarily
unstable.
IEMR bits YUV1 and YUV0 retain their values in a reset.
Bits 15 to 2—Reserved: Only 0 should be written to these bits.
Bits 1 and 0—YUV Mode (YUV1, YUV0): These bits specify conversion to RGB
format, and storage in the UGM, of data input in YUV or ∆YUV format.
Bit 1: Bit 0:
Y U V 1 Y U V 0
0 0
1
1 0
1
144
12 11 10 9
— — — —
— — — —
— — — —
Description
Normal mode is set. Data conversion is not performed.
YUV-RGB conversion is performed. When the total number of data
conversion pixels reaches 0, this bit is automatically cleared and normal
mode is entered. The total number of data conversion pixels is the
product of the image data size register X and Y (IDSRX, IDSRY) set
values. The total number of data conversion pixels is decremented by 1
in the LSI each time a pixel is processed.
UGM access by the CPU is disabled in this mode.
∆YUV-RGB conversion is performed. When the total number of data
conversion pixels reaches 0, this bit is automatically cleared and normal
mode is entered. The total number of data conversion pixels is the
product of the image data size register X and Y (IDSRX, IDSRY) set
values. The total number of data conversion pixels is decremented by 1
in the LSI each time a pixel is processed.
UGM access by the CPU is disabled in this mode.
Setting prohibited
8 7 6 5 4
— — — — —
— — — — —
— — — — —
3 2 1 0
— YUV1 YUV0
—
— — * *
— — R/W R/W