Hitachi HD64411 Q2 User Manual page 189

(4) CPU Write Cycle
Table 7-7 CPU Write Cycle
I t e m
Address Setup Time
Address Hold Time
CSn Setup Time
CSn Hold Time
RD "High" Level Width
WAIT Delay Time
WEn "High" Level Setup
Time
WAIT Cycle Start Time 2
WEn "High" Level Width
Write Data Setup Time For
WEn
Write Data Hold Time
Write Data Turn Off Time
WEn "High" Level Hold Time t
Notes: 1. If the fall of CSn is later than the fall of WEn , the specifications of t
are from the fall of CSn. (CSn = CS0, CS1. WEn = WE0 , WE1 .)
2. If the rise of CSn is earlier than the rise of WEn , the specifications of t
t , and t
WRDH WRDOF
3. WEn = WE0 , WE1
182
Symbol Min
t 0
ADS
t 0
ADH
t 0
CSS
t 0
CSH
t t
RDHW cyc0
t —
WAD
1/2 ×
t
WES
t – 9
cyc0
t —
WAS2
t t
WEHW cyc0
t 2
WRDES tcyc0
t 0
WRDH
t —
WRDOF
12 – 1/2 ×
WEH
t
cyc0
are from the rise of CSn. (CSn = CS0, CS1. WEn = WE0 , WE1 .)
T e s t
M a x Unit Conditions N o t e s
— ns Figure 7-7
— ns
— ns
— ns
— ns
25 ns
— ns
4t ns
cyc0
— ns
— ns
— ns
30 ns
— ns
1
2
3
Multiplica-
tion off
3
3
3
Multiplica-
tion off
, t , and t
ADS RDHW WAS2
, t , t ,
ADH RDHW WRDES